1. Field of the Invention
The present invention is related to the field of frequency synthesizers used in zone bit recording schemes for disk drives.
2. Background Art
Frequency synthesizers are used in time based generators implemented in disk drive systems that use zone bit recording schemes. In a zone bit recording scheme, data is written onto the media of a data disk at different frequencies according to the concentric zones of the data disk. In zones that are located near the outer circumference of the disk, the linear track length of the zone is longer than that of a zone located at an inner circumference. This is due to the greater zone circumference. In order to maintain a constant bit density in all zones, data is written at higher frequencies in zones near the outer circumference of the disk, whereas data is written at lower frequencies in zones near the inner circumference of the disk. In such applications, frequency synthesizers are used to implement the different write and read frequencies. When switching from one zone to another, the frequency synthesizer is reset to a frequency appropriate for the new zone.
A time base generator (TBG) is a phase-locked loop (PLL) based circuit that provides a programmable reference frequency for constant density recording applications. The time base generator requires a loop filter to control its PLL locking characteristic. In read, write and idle modes, the TBG provides a stable frequency. The synthesized frequency is programmed using two registers of the TBG. These registers are referred to as the M and N registers of the TBG.
The time based generator comprises a PLL circuit. In general, a PLL circuit acquires the nominal frequency of a reference signal and tracks deviations in its nominal frequency. The PLL produces an output clock frequency that varies according to deviations of the reference frequency. In order to track the reference signal frequency, the PLL circuit compares the phase of a signal dependent on the reference signal to the phase of a signal dependent on the PLL output signal. The difference in phase between the two frequencies produces an error signal that drives a voltage controlled oscillator (VCO) of the PLL, thereby forcing the VCO output frequency to follow changes in the reference frequency. In TBG circuits, the reference signal is a fixed frequency signal and the VCO center frequency is controlled by a control current (or voltage) as described below.
FIG. 1 is a block diagram of a prior art circuit for implementing a frequency synthesizer comprising divide-by-N and divide-by-M counters 110 and 170, phase detector 120, charge pump 130, loop filter 140, VCO amplifier 150, VCO 160 and digital-to-analog converter (DAC) 180. The circuit illustrated in FIG. 1 is a frequency synthesizer for providing a VCO output signal 190 that is dependent upon a reference signal 102 and divide-by-N and divide-by-M counters 110 and 170. Reference signal 102 and N input 104 are provided to divide-by-N counter 110. The output 114 of divide-by-N counter 110 provides EQ.PHI.N signal 116 and is coupled to a first input of phase detector 120. M input 106 is provided to divide-by-M counter 170. The output 172 of divide-by-M counter 170 provides EQ.PHI.M signal 176 and is coupled to a second input of phase detector 120. A first output 122 of phase detector 120 is coupled to a first input of charge pump 130 and provides a pump up (PU) signal 126. A second output 124 of phase detector 120 is coupled to a second input of charge pump 130 and provides a pump down (PD) signal 128.
Charge pump 130 provides an output 132 which is coupled to loop-filter 140 and to a first input of VCO amplifier 150. Loop filter 140 provides loop voltage 142 to VCO amplifier 150. The output 152 of VCO amplifier 150 provides adjust voltage 154 and is coupled to a first input of VCO 160. The output 162 of VCO 160 is coupled to a first input of divide-by-M counter 170 and provides VCO output signal 190. An M input 106 is provided to a second input of divide-by-M counter 170. Reference current 108 and data rate (DR) input 112 are provided to first and second inputs of DAC 180, respectively. The outputs 182, 184 and 186 are coupled to second inputs of charge pump 130, VCO amplifier 150 and VCO 160, respectively, and provide currents I.sub.CP, I.sub.BG and I.sub.BS to charge pump 130, VCO amplifier 150 and VCO 160, respectively.
N input 104 is an N+1 bit value provided to divide-by-N counter 110. The output 114 of divide-by-N counter 110 is EQ.PHI.N signal 116 having a frequency, f.sub.REF .div.N, where f.sub.REF is the reference frequency of reference signal 102. M input 106 is an M+1 bit value provided to divide-by-M counter 170. The output 172 of divide-by-M counter 170 is EQ.PHI.M signal 176 having a frequency, f.sub.VCO .div.M, where f.sub.VCO is the frequency of VCO output signal 190. Phase detector 120 compares frequency f.sub.REF .div.N of EQ.PHI.N signal 116 to the frequency f.sub.VCO .div.M of EQ.PHI.M signal 176 provided to the second input of phase detector 110. Phase detector 110 generates one of two signals, pump up signal 126 or pump down signal 128, indicating the difference in phase between EQ.PHI.N signal 116 and EQ.PHI.M signal 176. If EQ.PHI.N signal 116 is higher in frequency than EQ.PHI.M signal 176, phase detector 120 outputs a pulse(s) on pump up signal 126 to increase the frequency f.sub.VCO of VCO output signal 190. Analogously, if EQ.PHI.N signal 116 is lower in frequency than EQ.PHI.M signal 176, phase detector 120 outputs a pulse(s) on pump down signal 128 to decrease the frequency f.sub.VCO of VCO output signal 190.
Pump up signal 126 and pump down signal 128 are provided to charge pump 130 which generates an output current 132 in response to the signals. Charge pump 130 is well-known in the art and therefore is not shown in greater detail. Output current 132 of charge pump 130 is provided to loop filter 140 which produces loop voltage 142 in response. Pump Lip signal 126 causes charge pump 130 to increase loop voltage 142 generated by loop filter 140 by sourcing output current 132, whereas pump down signal 128 reduces loop voltage 142 by sinking output current 132 provided to loop filter 140. Thus, pump up signal 126 and pump down signal 128 act to provide current pulses for output 132 of charge pump 130. This is affected by transferring charge through transistor action in response to the pump up and pump down signals 126-128, respectively.
As is well-known in the art, output 182 of DAC 180 provides charge pump current I.sub.CP to charge pump 130 thereby controlling the rate at which charge pump 130 changes the loop voltage provided by loop filter 140. In time base generator applications, the circuit of FIG. 1 provides a higher frequency VCO output frequency at outer concentric zones and therefore loop filter 140 must provide more rapid changes in loop voltage 142 that controls VCO 160 in order to track reference signal 102. Thus, charge pump current I.sub.CP controls the current levels of output current 132 provided to loop filter 140.
The analog voltage generated by loop filter 140 is provided to VCO amplifier 150. VCO amplifier 150 accordingly attenuates or amplifies loop voltage 142 in order to drive VCO 160. The output 152 of VCO amplifier 150 is coupled to a first input of VCO 160. The output 152 of VCO amplifier 150 causes VCO 160 to produce VCO output signal 190 having a corresponding frequency f.sub.VCO. VCO output signal 190 is provided to a first input of divide-by-M counter 170. Divide-by-M counter 170 generates EQ.PHI.M signal 176 having a frequency equal to f.sub.VCO .div.M.
Reference current 108 is provided to DAC 180 and is used to set the current levels of currents I.sub.CP, I.sub.BG and I.sub.BS provided by outputs 182, 184 and 186 of DAC 180, respectively. DR input 112 provided to DAC 180 is a P+1 bit digital value that further controls the current levels of currents I.sub.CP, I.sub.BG and I.sub.BS provided by outputs 182, 184 and 186 of DAC 180, respectively. In general, currents I.sub.CP and I.sub.BG are determined by data rate input 112 while current I.sub.BS is constant. In particular applications, current I.sub.BS is also programmable according to DR input 112. Current I.sub.BS sets the center frequency of VCO 160.
Once the frequency f.sub.VCO .div.M of EQ.PHI.M signal 176 becomes equal to, or captures, the frequency f.sub.REF .div.N of EQ.PHI.N signal 116, the PLL produces a dependent frequency for VCO output signal 190 over a range of frequencies referred to as the lock range. The lock range is the range of phase values for the difference in phase between EQ.PHI.N and EQ.PHI.M signals 116 and 176 that produces an appropriate voltage level at the output 152 of VCO amplifier 150. In general, the lock range forces frequency f.sub.VCO of VCO output signal 190 to track frequency f.sub.REF of reference signal 102.
FIGS. 4-6 are timing diagrams illustrating signals for operating the prior art frequency synthesizer of FIG. 1. FIG. 4A is a timing diagram illustrating the operation of divide-by-N counter 110. Reference signal 102 clocks the operation of divide-by-N counter 110. The internal value 410 of divide-by-N counter 110 is illustrated in FIG. 4A with respect to reference signal 102. Transitions in the internal value 410 of divide-by-N counter 110 are indicated with an X in the drawing. At time T1, the rising edge reference signal 102 clocks divide-by-N counter 110 producing an internal value 410 of l. At time T2, divide-by-N counter 110 is decremented to l-1 for its internal value 410. Reference signal 102 continues to clock divide-by-N counter 110, thereby decrementing the internal value 410 of divide-by-N counter 110. At time T3, the internal value 410 of divide-by-N counter 110 is decremented from 1 to 0, thereby forcing EQ.PHI.N signal 116 to logic high. EQ.PHI.N signal 116 remains high for one clock cycle of reference signal 102 and has a transition to logic low at time T4. At time T4, the internal value 410 of divide-by-N counter 110 is set to N and commences counting again. A disadvantage of this prior art counter is that if a new N input 104 provided to divide-by-N counter 110 changes at time T4, the value of N becomes unpredictable. The divide-by-N counter 170 may load intermediate values at time T4 which drive the frequency synthesizer away from the desired output frequency of VCO) 160.
FIG. 4B is a timing diagram for divide-by-M counter 170. VCO output signal 190 clocks divide-by-M counter 170. Divide-by-M counter 170 operates analogously to the description above for FIG. 4A. Thus, if a new M input 106 provided to divide-by-M counter 170 changes at time T4, the value of M becomes unpredictable. The divide-by-M counter 170 may load intermediate values at time T4 which drive the frequency synthesizer away from the desired output frequency of VCO 160.
FIG. 5 is a timing diagram illustrating the operation of phase detector 120. EQ.PHI.N signal 116 generated by divide-by-N counter 110 is set logic high at time T1, thereby, producing a rising edge transition in pump up signal 126. Phase detector 120 sets pump up signal 126 to logic high at time T1. At time T2, pump signal 126 is set low by phase detector 120 while EQ.PHI.M signal 176 becomes high. This produces a glitch in pump down signal 128 when phase detector 120 is reset at time T2. At time T3, EQ.PHI.M signal 128 is set high producing a logic level high in pump down signal 128 output by phase detector 120. At time T4, pump down signal 128 is set to logic level low while EQ.PHI.N signal 116 is set logic high. Because EQ.PHI.N signal 116 is high at time T4, a small glitch appears in the pump up signal 126 when phase detector 120 is reset. At time T5, both EQ.PHI.N and EQ.PHI.M signals 116 and 176 are set high by counters 110 and 170, respectively, thereby producing glitches in pump up and pump down signals 126 and 128.
The glitches illustrated in FIG. 5 at times T1-T5 are artifacts of phase detector 120. The glitches are intended to insure that phase detector does not have a dead band. A dead band occurs when the phases of EQ.PHI.N and EQ.PHI.M signals 116 and 176 are very close to one another, thereby producing zero phase difference at the output of the phase detector. This causes the PLL to drift away from lock on reference signal 102 because an appropriate loop voltage 142 is not produced in response to the approximately zero phase difference.
FIG. 6 is a timing diagram illustrating charge pump current 132 and loop voltage 142 produced by charge pump 130 and loop filter 140, respectively, in response to pump up signal 126 and pump down signal 128. At time T1, pump up signal 126 is set high by phase detector 120. This causes charge pump 130 to output a positive current 132 to loop filter 140, thereby increasing positive loop voltage 142. Loop voltage 142 increases as long as pump up signal 126 remains high. At time T2, pump up signal 126 is set low, thereby setting charge pump current 132 to zero. Accordingly, loop voltage 142 begins to decay in amplitude. The glitch in pump down signal 128 at time T1 is suppressed by low pass filter 140. Similarly, at time T3, pump down signal 128 is asserted causing charge pump 130 to sink charge pump current 132. Therefore, loop filter 140 decreases loop voltage 142. Loop voltage 142 decreases until time T4 when pump down signal 128 is negated. Loop filter 140 suppresses the glitch in pump up signal 126 at time T4. At time T5, a glitch occurs in pump up signal 126 and pump down signal 128 (as illustrated in FIG. 5 when EQ.PHI.N and EQ.PHI.M signals 116 and 176 are both set high). The glitches are suppressed by filter 140.
The prior art circuit shown in FIG. 1 for implementing a frequency synthesizer includes counters 110 and 170 for controlling the output frequency of the frequency synthesizer. During a zone change, counters 110 and 170 are loaded with a new values (related to frequency information). A settling time must elapse for a digital-to-analog converter (DAC) and PLL to acquire lock before the frequency synthesizer begins generating the new frequency for VCO output signal 190. The frequency of the VCO output signal 190 is given by the following expression: EQU f.sub.VCO =f.sub.REF (M+1)/(N+1), (1)
where M and N are the values of M input 106 and N input 104 and f.sub.REF is the frequency of reference signal 102.
A disadvantage of this prior art scheme is that zone change-overs are performed without knowledge of loop voltage 142. If loop voltage 142 rails, predictions about the settling time are invalid and the system must wait a longer time to settle. This disadvantage of the prior art occurs when any one or all of the values stored in the registers/counters N, M and DR changes, causing the frequency synthesizer to behave unpredictably. The loop voltage, 142, adjustable voltage 154 and VCO output frequency f.sub.VCO are not predictable for a considerable amount of time. For this reason, the settling time and the ability of the frequency synthesizer to settle down to a new stable state cannot be predicted using classical PLL analysis. This unpredictable nature is due to the following factors: the loop voltage 142 and adjustable voltage 152 rail to a supply voltage level when transistors in each device saturate. The charge pump, VCO control circuit and VCO may not behave linearly (i.e., shutdown, saturate or rail). Linear response of each block is required to perform linear analysis for PLL operation.
Another disadvantage of the PLL circuit illustrated in FIG. 1 is that phase detector 120, loop filter 140 and VCO 160 are designed with a constraint of requiring a "graceful failure mechanism" when PLL circuit operation nears non-linear operation. The requirements for a graceful failure mechanism are: 1) the circuit must not latchup, 2) must not become unstable (i.e., undamped oscillation of the circuit) and 3) must be able to recover from the failed state without needing to remove power from the circuit.
A further disadvantage of the prior art circuit is an inability to predict the settling time if, in fact, the system can settle down. This inability to predict the settling time places an undue constraint and response time on systems using this type of frequency synthesizer.
Still another disadvantage of the prior art circuit is that the divide-by-N and divide-by-M counters may load extraneous, incorrect values that are neither the old or the new values to be loaded into the counters. This forces the phase-locked loop circuit to phase compare signals with the wrong phase for at least one phase comparison cycle. During the error time when the divide-by-N or divide-by-M counter 110 or 170 is counting using the wrong value, the phase-locked loop circuit is driven away from the intended final state of the PLL. Again, the prior art circuit requires longer settling times and may become unstable, and may never recover from the transient and settle.